As the semiconductor industry introduces new generations of integrated circuits (ICs) having higher performance and greater functionality, the density of the elements that form the ICs is increased, while the dimensions and spacing between components or elements of the ICs are reduced. As components become smaller and patterning techniques become more precise, reducing overlay errors of the exposed pattern and the underlying pattern becomes more important. Accordingly, what is needed is a method for improving alignment accuracy in the patterning process used to expose a substrate such as a semiconductor wafer.